module rc_field #(
    parameter WD   = 32,
    parameter RST  = {WD{1'b0}}
)(
    input  clk,
    input  rst_n,

    input  cpu_en,
    input  cpu_r_en,

    input  rtl_wen,
    input  [WD -1:0]rtl_wdata,

    output [WD -1:0]rdata
);

wire cpu_ren = cpu_en && cpu_r_en;

reg [WD -1:0]field;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        field <= RST;
    else if(rtl_wen)
        field <= rtl_wdata;
    else if(cpu_ren)
        field <= RST;
end

assign rdata = field;

endmodule
